As integration of semiconductor devices increases and multi-layer interconnection processes are more readily applied, global planarization of interlayer dielectric layers is becoming increasingly important. While variable techniques have been used for the global planarization, CMP processes have been widely used in recent years due to numerous well-known advantages.
On the other hand, using the CMP process generates process dispersion, which usually result from changes in characteristics of dissipative parts such as pads, slurry, and heads. When use of the CMP process generates poor dispersion, adverse effects on performance and yield of products may result. For this reason, in the case of conventional CMP processes, a sample lot is polished by the CMP beforehand. The process time of polishing the sample lot is calculated and is then applied when a main lot is polished by the CMP. However, because this method is greatly influenced by prior factors, accuracy of a pre-set process time can vary depending on operator experience or ability. To overcome this problem, a method of controlling a process time was proposed, in which, although characteristics of a CMP apparatus change with time, a CMP time based on the latest characteristics of the CMP apparatus is applied. The method is disclosed in Korean Patent Publication No. 2001-55689 entitled “A METHOD OF CONTROLLING THE CMP TIME.”
FIGS. 1 to 4 are cross-sectional views illustrating a conventional CMP process.
The conventional CMP is divided into a process of planarizing an insulation layer and a process of forming a pattern. The process of forming a pattern comprises forming a polishing target layer on the patterned insulation layer and polishing the polishing target layer until the insulation layer is exposed, in order to form a contact plug, a capacitor electrode, or a metal interconnection. When a pattern is formed using the CMP, it is important that the polishing target layer does not remain on the insulation layer. Generally, an upper portion of the insulation layer is over-etched to prevent the polishing target layer from remaining on the insulation layer. An over-etched thickness is measured from a thickness of the insulation layer before and after the CMP. The over-etched thickness is compared with a reference value and this enables correction of a CMP time. Also, the corrected CMP time may be applied to a subsequent substrate. As a result, a process deviation of the CMP can be reduced.
Referring to FIG. 1, main patterns 8 are disposed on a main region b of a semiconductor substrate 1 where circuits or devices will be formed. Test patterns 2 for monitoring a process state of the main region b are disposed at a predetermined region of the semiconductor substrate 1. Generally, the test patterns 2 are disposed at a monitoring region a, which is positioned on a scribe line between the main regions b. Each test pattern 2 is formed to various shapes depending on monitoring processes.
Referring to FIGS. 2 and 3, a CMP target layer 10 is formed on an entire surface of the semiconductor substrate 1 where the test pattern 2 and the main pattern 8 are formed. Continuously, the CMP target layer 10 is polished to expose the main pattern 8 and the test pattern 2. Thus, an interconnection 12 is formed to fill a space between the main patterns 8. The main region b generally includes a region 8a of a high pattern density as well as a region 8b of a low pattern density. In addition, because the conventional test pattern 2 is formed for the purpose of measuring a thickness, the test pattern 2 is planarized unlike the main pattern 8. According to the CMP process, the polishing target layer 10 is polished by providing slurry having a high etch selectivity to the polishing target layer 10. Therefore, when the CMP process is performed, a polishing rate is dependant on a pattern density.
As illustrated in FIG. 4, after the CMP, an etched thickness of the test pattern 2 differs from that of the main pattern 8. In general, a thickness of the test pattern 2 is measured before and after the CMP in order to monitor the process. Thus, even though an etched thickness is measured to be appropriate, it is difficult to rely on a process state of the main region. In other words, it is possible that the main pattern 8 is unnecessarily over-etched according to a pattern density of each region of the main region b (see 16 of FIG. 4). Otherwise, the polishing target layer 10 may remain on the main pattern 8 (see 14 of FIG. 4).
Similar to the metal interconnection process, in the case where the polishing target layer 10 is composed of metals, a thickness of the test pattern 2 cannot be measured just before the CMP, because the test pattern 2 is covered with the polishing target layer 10. Thus, a thickness of the test pattern 2 should be measured before forming the polishing target layer 10. However, a cleaning process, which is performed before forming the polishing target layer 10, causes a change in the thickness of the test pattern 2. Consequently, an over-etched thickness of the test pattern 2 may be measured with low reliability.